Recently, as display devices, liquid crystal display (LCD) devices that feature thinness, lightweight, lower power consumption have been widespread used, and have been extensively utilized as display units of mobile devices including portable telephone apparatuses (such as mobile phones or cellular phones), PDAs (personal digital assistants), and notebook PCs. Recently, however, a technology for supporting a larger screen and a moving image of the liquid crystal display devices has been developed. Then, realization of tabletop large-screen display devices and tabletop large-screen liquid crystal TVs as well as display devices and TVs for mobile use have become possible. As these liquid crystal display devices, an active matrix driving system liquid crystal display device capable of performing high-definition display is employed.
First, referring to FIG. 25, a typical configuration of the active matrix driving system liquid crystal display device will be outlined. FIG. 25 schematically shows a main configuration connected to one pixel in a liquid crystal display unit, using an equivalent circuit.
Generally, a display unit 960 of the active matrix driving liquid crystal display device includes a semiconductor substrate, an opposing substrate, and a liquid crystal sealed in between these two substrates by opposing these two substrates. On the semiconductor substrate, transparent pixel electrodes 964 and thin-film transistors (TFTs) 963 are arranged in a matrix form (of 1280×3 pixel rows×1024 pixel columns in the case of a color SXGA panel, for example). One transparent electrode 966 is formed on an entire surface of the opposing substrate.
Turning on and off of a TFT 963 having a switching function is controlled by a scan signal. When the TFT 963 is turned on, a gray scale voltage corresponding to a video signal is applied to a corresponding pixel electrode 964. Transmittance of the liquid crystal is changed by a potential difference between each pixel electrode 964 and the opposing substrate electrode 966, and the potential difference is held by a liquid crystal capacitance 965 for a certain period, thereby displaying an image.
On the semiconductor substrate, data lines 962 and scan lines 961 are wired in the form of a grid (in which 1280×3 data lines and 1024 scan lines are arranged in the case of the color SXGA panel described above). A data line 962 sends a plurality of level voltages (gray scale voltages) applied to each pixel electrode 964, and a scan line 961 sends the scan signal. Due to a capacitance produced at an intersection between each of the scan lines 961 and each of the data lines 962 and a liquid crystal capacitance sandwiched between the semiconductor substrate and the opposing substrate, the scan lines 961 and the data lines 962 have become a large capacitive load.
The scan signal is supplied to a scan line 961 from a gate driver 970, and a gray scale voltage is supplied to each pixel electrode 964 from a data driver 980 through a data line 962.
Rewriting of data of one screen is usually performed in one frame period (of approximately 1/60 seconds). Data is successively selected every pixel row (every line) by each scan line, and a gray scale voltage is supplied from each data line within a selection period.
While the gate driver 970 should supply the scan signal of at least two values, the data driver 980 needs to drive a data line by the gray scale voltage of multi-valued levels corresponding to the number of gray scales. For this reason, the data driver 980 includes a decoder that converts video data to a gray scale voltage signal and a digital-to-analog converter circuit (DAC) formed of an operational amplifier that amplifies a voltage of the gray scale voltage signal, for output to a corresponding data line 962.
Recently, image quality of liquid crystal display devices has been improved (or the number of colors used in the liquid crystal display devices has been increased). There has been a growing demand for at least 260 thousand colors (video data of six bits for each of colors of R, G, B) and 16,770 thousand colors (video data of eight bits for each of the colors of R, G, B), and 1,074,000 thousand colors (video data of 10 bits for each of the colors of R, G, B) or more.
For this reason, for a data driver that outputs a gray scale voltage corresponding to multi-bit video data, a voltage output with high accuracy is demanded. In addition, the number of devices in a circuit portion that handles the video data has increased, and the chip area of a data driver LSI has increased, which has become a factor in resulting in high cost. This problem will be described below in detail.
FIG. 26 is a diagram showing a configuration of the data driver 980 in FIG. 25, and showing a main portion of the data driver 980 using blocks. Referring to FIG. 26, the data driver 980 is configured by including a latch address selector 981, a latch 982, a reference voltage generation circuit (gray scale voltage generation circuit) 983, decoders 984, and amplifiers (buffer circuits) 985.
Based on a clock signal CLK, the latch address selector 981 determines a data latch timing. The latch 982 latches digital video data based on the timing determined by the latch address selector 981, and outputs the data to each of the decoders 984 in response to an STB signal (strobe signal) in unison. The reference voltage generation circuit 983 generates reference voltages (gray scale voltages) the number of which is the number of gray scales corresponding to the video data. Each decoder 984 selects one of the reference voltages corresponding to input data and outputs the selected reference voltage. Each of the amplifiers 985 receives the gray scale voltage output from a corresponding one of the decoders 984 and performs current amplification, for output as an output voltage Vout.
When 6-bit video data is input, the number of gray scales is 64. Then, the reference voltage generation circuit 983 generates the reference voltages (gray scale voltages) of 64 levels. The decoder 984 has a circuit configuration in which the decoder 984 selects one gray scale voltage from among the gray scale voltages of 64 levels.
On the other hand, when 8-bit video data is input, the number of gray scales becomes 256. Then, the reference voltage generation circuit 983 generates the reference voltages (gray scale voltages) of 256 levels. The decoder 984 has a circuit configuration in which the decoder 984 selects one gray scale voltage from among the gray scale voltages of 256 levels.
On the other hand, when 10-bit video data is input, the number of gray scales becomes 1024. Then, the reference voltage generation circuit 983 generates the reference voltages (gray scale voltages) of 1024 levels. The decoder 984 has a circuit configuration in which the decoder 984 selects one gray scale voltage from among the gray scale voltages of 1024 levels.
As described above, when the number of bits of video data is increased, a circuit size of each of the reference voltage generation circuit 983 and the decoders 984 increases. When the video data is increased from six bits to eight bits, the circuit size becomes not less than four times of that for six bits. When the video data is increased from six bits to 10 bits, the circuit size becomes not less than 16 times of that for six bits.
Accordingly, the chip area of the data driver LSI is increased, thus leading to high cost due to an increase in bits of the video data.
On contrast therewith, as a technology for restraining an increase in the chip area of the data driver LSI even if the number of bits of video data is increased, a description in U.S. Pat. No. 6,246,351 (Patent Document 1) is referred to.
FIG. 27 is a diagram for explaining the technology disclosed in Patent Document 1 (corresponding to FIG. 2 in Patent Document 1). Referring to FIG. 27, a DAC in FIG. 27 is formed of a string DAC unit (decoder unit) 4001 and an interpolating amplifier unit 4100. The string DAC unit (decoder unit) 4001 includes a string constituted from a set of resistance elements R000 to R255 and switches S000 to S255 which select a set of voltages at both ends of a resistance. The interpolating amplifier unit 4100 includes a differential amplifier including a plurality of differential pairs of the same polarity and switches 4004 for selectively receiving voltages supplied to two input terminals 4002 and 4003 to non-inverting inputs of the differential amplifier.
In the string DAC unit 4001, by the switches S000 to S255 controlled by higher-order M bits of digital data, two voltages at both ends of one resistance among the resistance elements R000 to R255 of the resistor string are selected. Then, the selected voltages are supplied to input terminals 4002 and 4003 of the interpolating amplifier unit 4100, respectively.
The two voltages selected by the switches are limited to the voltages at both ends of the one resistance among the resistance elements R000 to R255 of the resistor string. Voltages at both ends of a plurality of the resistance elements are not selected, or the same voltage is not selected.
The interpolating amplifier unit 4100 selectively inputs voltages V1 and V2 supplied to the input terminals 4002 and 4003, respectively, to non-inverting inputs 4111, 4121, 4131, and 4141 by the switches 4004 controlled by lower-order N bits of the digital data, and can output a voltage obtained by internally dividing the voltages V1 and V2 at an arbitrary ratio, according to a ratio between the number of the voltages V1 and the number of the voltages V2. The non-inverting input 4111 of a differential pair 4110 is connected to the input terminal 4002. An output terminal Vout is feedback connected to an inverting input 4112 of the differential pair 4110, an inverting input 4122 of a differential pair 4120, an inverting input 4232 of a differential pair 4130, and an inverting input 4142 of a differential pair 4140.
Since the four differential pairs (4110, 4120, 4130, 4140) are provided in FIG. 27, voltages obtained by internally dividing the voltage V1 at the terminal 4002 and the voltage V2 at the terminal 4003 at a ratio of 1:3, 1:1, and 3:1 and four voltages of a voltage Vin2 can be output, due to an LSB (Least Significant Bit).
Accordingly, for the number of voltage levels to be output, the number of input voltage levels can be reduced to even the inverse of the number of differential pairs. For this reason, the number of power supply lines of the string DAC unit and the area of the string DAC unit can be reduced.
A technology for implementing an increase in accuracy of an output voltage in addition to area saving of a data driver, a configuration in FIG. 15 of JP Patent Kokai Publication No. JP-P-2001-343948A (Patent Document 2), for example, can be pointed out.
FIG. 28 shows an example of a configuration of an amplifier circuit in an output unit of a data driver corresponding to the configuration in FIG. 15 in the document described above. Referring to FIG. 28, the amplifier circuit is configured by including an amplifier 85-1 and a switch circuit 42. The amplifier 85-1 is the amplifier capable of outputting a voltage obtained by 1:1 internal division of voltages input to terminals IN1 and IN2 to a terminal OUT. Since the number of input power supply lines can be reduced to a half of the number of voltage levels to be output, the area of a DAC portion can be reduced. Connection among each of differential input terminals for the amplifier, each of the terminals IN1 and IN2, and output terminal OUT is controlled by the switch circuit 42, and can assume the following four states.
(1) First State:
Terminals Q12 and Q13 are connected to the terminals IN1 and IN2, respectively. Terminals Q11 and Q14 are connected to the output terminal OUT.
(2) Second State:
The terminals Q12 and Q13 are connected to the terminals IN2 and IN1, respectively. The terminals Q11 and Q14 are connected to the output terminal OUT.
(3) Third State:
The terminals Q11 and Q14 are connected to the terminals IN1 and IN2, respectively. The terminals Q12 and Q13 are connected to the output terminal OUT.
(4) Fourth State:
The terminals Q11 and Q14 are connected to the terminals IN2 and IN1, respectively. The terminals Q12 and Q13 are connected to the output terminal OUT.
Then, the four states described above are switched according to a predetermined cycle. An output offset caused by threshold value variations of transistors forming the amplifier 85-1 is time averaged, and cancelled.
Accordingly, by using the configuration in FIG. 28, the area of the DAC portion can be reduced. An output accuracy of the amplifier 85-1 can also be improved.
However, it is inferred that, since two gray scale voltages are supplied to non-inverting input terminals in the third and fourth states in the configuration in FIG. 28, the data driver cannot output a desired voltage properly.
In the case of FIG. 28, it is inferred that when the first and second states are switched, there is a certain effect on cancellation of the output offset.    [Patent Document 1]    U.S. Pat. No. 6,246,351 (FIG. 2)    [Patent Document 2]    JP Patent Kokai Publication No. JP-P-2001-343948A (FIG. 15)